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Course Overview
PART I: REVIEW OF LOGIC DESIGN
Gates
Multiplexer/Demultiplexer (Mux/Demux)
Design Example: Register File
Design Example: Decrementer
Design Example: Four Deep FIFO
PART II: VERILOG FOR SYNTHESIS
Verilog code for Gates
Verilog code for Multiplexer/Demultiplexer
Verilog code for Adder, Subtractor and Multiplier
Declarations in Verilog, reg vs wire
Arrays
PART III: VERILOG FOR SIMULATION
Verilog code for Testbench
Generating test signals (repeat loops, $display, $stop)
Simulations Tools overview
Verilog simulation using Xilinx Vivado
PART IV: VERILOG SYNTHESIS USING XILINX VIVADO
Design Example
Adding Constraint File
Synthesizing design
Adding Board files
PART V: STATE MACHINES USING VERILOG
One-Hot encoding
Beginning & Intro
SPICE & Verilog-A
Verilog , Verilog-A , Verilog-AMS
Conservative Modeling & Code Example
EP-2 Beginning & Chapter Index
Derived Nature
String & Real Datatypes in Verilog-A
Types of Branches
Comments in Verilog-A
Assignment Operator & Statement
Four Types of Controlled Sources in Verilog-A
Display Functions ($strobe, $write , $display, $monitor)
If & Else-If
Repeat Statement
Generate Statement
User Defined Function : Restrictions & Example
Analog Operators : Restrictions
Transition Operator a.k.a Transition Filter
initial_step & @final_step
Composite Example : @initial_step , @timer & @final_step
Last Crossing Theory & Example
Discontinuity Example-1
Include Files & Defining Macros
Connect Modules
Connect Rules